Full-time jobs in Richmond, British Columbia

Find full-time jobs in Richmond, British Columbia and nearby towns within 25 km. Read the full details and apply.

Newest first

Within 25 km of Richmond

Added 15 days ago
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Added 15 days ago
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Vancouver, BC
Added 15 days ago
Manager, IT Operations & Services
MatchBox Consulting Group
Vancouver, BC
Added 15 days ago
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Burnaby, BC
- $65,000 to $75,000 CAD / year
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Vancouver, BC
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Lead Consultant - Oracle Fusion SCM
Infosys
Vancouver, BC
Added 15 days ago
Technology Lead- Memory Layout
Infosys
Burnaby, BC
Added 15 days ago
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Vancouver, BC
Added 15 days ago
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Richmond, BC
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Medical Office Assistant
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Vancouver, BC
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Burnaby, BC
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barista - Store# 00185, CAMBIE & 19TH
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Vancouver, BC
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Burnaby, BC
Added 15 days ago
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Vancouver, BC
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Vancouver, BC
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Burnaby, BC
Added 15 days ago
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Vancouver, BC
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Infosys

Technology Lead- Memory Layout

Burnaby, BC, Canada

Full-time

Within 25 km of Richmond · About 15.2 km from the city centre

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Job details

Job type: Full-time
Apply by: Nov 12, 2026
Education: Bachelor’s degree
Posted: Oct 13, 2026

Original job description

Infosys is hiring Memory Team Layout. You will work along our Registers and Memory Arrays and Memory data path layout and design engineers .Based on the schematic shared you should be able to take it forward and collaborate with circuit team etc to create best layout possible.

Required Qualifications

Candidate must be located within commuting distance of Vancouver BC, Canada or be willing to relocate to the area. This position may require travel in Canada.
Bachelor’s degree or foreign equivalent required from an accredited institution. Will also consider three years of progressive experience in the specialty in lieu of every year of education.
At least 4 years of Information Technology experience.
Candidates authorized to work for any employer in the Canada without employer-based visa sponsorship are welcome to apply. Infosys is unable to provide immigration sponsorship for this role at this time.

Required Skills

Minimum Qualifications 5+ years of experience in Compiler/Custom Memory Layout design.
Memory Leafcell layout library design from scratch including top level integration.
Good knowledge on diAerent types of memory architectures.
Good knowledge in optimized layout design for better performance.
Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations.
3nm, 5 nm exposure required Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.
Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow.

The job may also entail sitting as well as working at a computer for extended periods of time. Candidates should be able to effectively communicate by telephone, email, and face to face.

Estimated annual compensation range for the candidate based in the below location will be:

BC- $90450 to $136500

About Us

Infosys is a global leader in next-generation digital services and consulting. We enable clients in more than 50 countries to navigate their digital transformation. With over four decades of experience in managing the systems and workings of global enterprises, we expertly steer our clients through their digital journey. We do it by enabling the enterprise with an AI-powered core that helps prioritize the execution of change. We also empower the business with agile digital at scale to deliver unprecedented levels of performance and customer delight. Our always-on learning agenda drives their continuous improvement through building and transferring digital skills, expertise, and ideas from our innovation ecosystem.

EEO

Infosys provides equal employment opportunities to applicants and employees without regard to race; color; sex; gender identity; sexual orientation; religious practices and observances; national origin; pregnancy, childbirth, or related medical conditions; status as a protected veteran or spouse/family member of a protected veteran; or disability.

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More about this job

Responsibilities

Develop layouts for registers, memory arrays, and memory data paths based on schematics, collaborating with circuit design engineers. Create and integrate memory leaf cell layout libraries, optimizing layouts for performance and meeting physical verification requirements.

Requirements

Requires at least five years of compiler or custom memory layout design experience, including memory leaf cell library design and top-level integration, plus knowledge of memory architectures and optimized layout design. Candidates need hands-on FinFET experience, exposure to 3 nm or 5 nm technology, proficiency with physical verification and debugging, and experience using Cadence Virtuoso and Calibre; a bachelor's degree or equivalent is required, with qualifying experience accepted in lieu of education.

Skills

Compiler and Custom Memory Layout Design
Memory Architecture
Optimized Layout Design
FinFET Technology
Physical Verification
DRC
LVS
ERC
Boundary Condition Debugging
Cadence Virtuoso
Calibre
Top-Level Integration
Memory Data Path Layout

Visa sponsorship

Not detected in the job text

Keywords

Compiler
Custom Memory Layout
Memory Leaf Cell
Layout Library Design
Top-Level Integration
Memory Architecture
Memory Arrays
Registers
Memory Data Path
Circuit Design
FinFET
3 Nm
5 Nm
Physical Verification
DRC
LVS
ERC
Boundary Conditions
Cadence Virtuoso
Calibre
Layout Optimization
Schematic
Information Technology

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